In general, a data communications analyzer has at least two modes of operation, namely the monitor mode and the simulate mode. In the monitor mode, the analyzer receives the serial data that passes along a communications interface between two nodes of a data communication network, e. g. two computers, and observes passively the stream of data passing between the nodes. In the simulate mode, the analyzer becomes a node in the data communication network, and appears to other nodes to be, for example, a host computer or a terminal. Thus, in the simulate mode the analyzer is able to both send and receive serial data. In the monitor mode, and when receiving data in the simulate mode, the analyzer converts the received serial data into parallel form and examines the stream of parallel characters to identify the occurrence of particular character strings.
A known data communications analyzer comprises the functional elements shown within the dashed outline 14 in FIG. 1 of the accompanying drawings. The known analyzer includes a main processor 2 that has a data bus 4, a read only memory (ROM) 6 that contains the firmware for operation of the processor 2, a read/write memory 8, a serial/parallel interface device 10 and a user interface 12. The main processor is a Z80 microprocessor and the serial/parallel interface 10 is a Z80 SIO (serial in out) peripheral. The user interface 12 comprises a keyboard and a display, and includes its own processor. At the start of a test, the operator of the analyzer enters information into the keyboard defining characters that the network under test is to be examined for. These test characters are transmitted to the main processor 2, which loads them into the memory 8. During the test, the analyzer receives serial data, for example through an RS-232C port. The SIO 10 assembles the serial data into a stream of parallel data characters and, acting through normal interrupt routines, places those data characters on the data bus 4 and transmits them to the main processor 2. In order to determine whether a data character is the same as a test character, the processor fetches a test character from the memory 8 and compares it with the data character. If the test is to locate a set of characters in a predetermined order, the processor 2 examines the stream of data characters until it identifies a coincidence with the first test character, and then it examines the next data character to determine whether there is a coincidence with the second test character. If there is no coincidence, the test is started again, looking for a data character that is the same as the first test character, but if coincidence is found, the next data character is examined against the third test character, and so on. If the data character stream includes a sequence of characters that is the same as the test character string, the processor 2 causes the processor to generate display codes that are sent to the user interface 12 to cause the display to provide an appropriate visual message.
In addition to examining the data character stream for a sequence of characters that is the same as the test character string, the analyzer may examine the data character stream for an end of frame (EOF) character or character string. When the EOF character or string of characters is identified, an appropriate report is generated and a display code is transmitted to the user interface 12 in response to the report.
During a test, the data characters that have been received are loaded by the main processor 2 into a capture buffer within the memory 8 for storage and subsequent review. Since the number of characters that can be stored is limited by the size of the capture buffer, the analyzer continuously monitors the data stream for the RR (receive ready) state that is used in the SDLC protocol, and rejects that state from entry into the capture buffer. This is because the RR state is frequently used as an idle condition, and it is not desirable that space in the capture buffer be taken up by characters that are not useful in analyzing operation of the network under test.
The maximum data rate that can be accommodated using the known analyzer is limited because the comparison between each data character and the appropriate test character is performed by a software routine, and the speed with which the comparison can be effected is limited by the operating speed of the processor. Moreover, the processor is also required to control the loading of data into the capture buffer and to generate the trigger reports.